1. Field of the Invention
This invention relates generally to a method for forming a four-transistor static-random-access-memory (SRAM) memory cell, and also is related to a structure of the four-transistors SRAM cell.
2. Description of the Prior Art
To meet customer demand for small size and low power products, manufacturers are producing newer integrated circuits (ICs) that operate with lower supply voltages and that include smaller internal subcircuits. Many ICs, such as memory circuits or other circuits such as microprocessors that include onboard memory, include one or more SRAM cells for data storage. SRAMs cells are popular because they operate at a higher speed than dynamic random-access-memory (DRAM) cells, and as long as they are powered, they can store data indefinitely, unlike DRAM cells, which must be periodically refreshed.
The conventional structure of the SRAM cell is a six-transistor SRAM cell, which means six transistors are used to form an SRAM cell. In general, advantages of the six-transistor SRAM at least include high speed and the possibility of low supply voltage. Unfortunately, one unavoidable disadvantage is that the area of the six-transistor SRAM cell is large, and the disadvantage is more serious and it is desired to overcome the disadvantage by either improving the structure of the six-transistor SRAM cell or providing a new SRAM cell. Therefore, four-transistors SRAM is present to replace the conventional six-transistors SRAM cell. Clearly, owing to the fact that the number of transistors is decreased, the occupied area of four-transistor SRAM cell is less than the six-transistor SRAM cell. Thus, the four-transistor SRAM cell is more suitable for ICs whenever the sizes of ICs are reduced, and even four-transistors also have some disadvantages such as higher off-state leakage current of PMOS. More background on four-transistor SRAM cell can be acquired by referring to IEEE IEDM 98-643 to IEDM 98-646, U.S. Pat. Nos. 5,943,269, 6,091,628, 6,044,011, 6,011,726, 5,751,044.
One ordinary circuit diagram of a four-transistor SRAM cell is shown in FIG. 1. The four-transistor SRAM cell, which is a loadless four-transistor SRAM cell, comprises first transistor 11, second transistor 12, third transistor 13 and fourth transistor 14. Moreover, source of third transistor 13 is electrically coupled with the drain of first transistor 11 and the gate of third transistor 13 is electrically coupled with drain of second transistor 12, source of fourth transistor 14 is electrically coupled with drain of second transistor 12 and gate of fourth transistor 14 is electrically coupled with drain of first transistor 11.
Leakage current of first transistor 11 and leakage current of second transistor 12 are not absolute zero, especially when first transistor 11/second transistor 12 are P-type transistors. An unavoidable shortage is that third transistor 13 is turned on by leakage current of second transistor 12 whenever both first transistor 11 and second transistor 12 are not totally turned off. Thus, whenever current is sent into the four-transistor SRAM cell for storing data, owing to both first transistor 11 and third transistor 13 being not totally turned off, current continually flows through first transistor 11 and third transistor 13. Significantly, continuous flow of current requires continuous supply of current, then stand-by current is not negligible and the four-transistor SRAM cell is less suitable for low power product.
An ordinary solution to this problem is increasing the threshold voltage of both third transistor 13 and fourth transistor 14 to prevent third transistor 13 (fourth transistor 14) being turned on by leakage current of second transistor 12 (first transistor 11). In this way, after numerous P-type transistors and numerous N-type transistors are formed in and on a substrate which at least includes a cell region and a periphery region, an additional implant mask (sometimes referred to as additional implant photoresist) is used to cover all P-type transistors and part of N-type transistors which are located in the periphery region, and then threshold voltages of part of N-type transistors which are located in said cell region is adjusted, for example, by an ion implanting process. Obviously, application of the additional implant mask not only complicates fabrication of the four-transistor SRAM but also increases cost of the four-transistor SRAM.
In short, the four-transistor SRAM still is not suitable for operation at low power supply, and corresponding improvement incorporates complicated fabrication and increased cost. Thus, it is desired to improve current fabrication, even the structure, of the four-transistor SRAM, to make the four-transistor SRAM more suitable for a low power device.
One main object of the invention is to present a method for forming a four-transistor SRAM cell without the application of an additional implant mask.
Another important object of the invention is to present a method for forming a four-transistor SRAM cell, whereby the adjusting process of some of the transistors are incorporated into the forming process of sources/drains of some transistors.
Still an essential object of the invention is to present a structure of a four-transistor SRAM cell, whereby the layout of the present structure is similar to a conventional structure, but the structures of transistors are different from conventional structures of transistors.
One preferred embodiment of the invention is a method for forming a four-transistor static-random-access-memory. The method comprises the steps of: providing a substrate which at least comprises a cell region and a periphery region, wherein the cell region comprises a first P-type region, a second P-type region, a first N-type region and a second N-type region, the periphery region comprises numerous periphery P-type regions and numerous periphery N-type regions; covering the first P-type region, the second P-type region and the periphery P-type regions by a first photoresist; forming numerous N-type sources and numerous N-type drains in the first N-type region, the second N-type region and the periphery N-type regions. Remove the first photoresist; using a second photoresist to cover the periphery N-type regions and some of the N-type drains which are located in both the first N-type region and the second N-type region; performing a large angle implanting process to form numerous P-type enlarged drains and numerous P-type enlarged sources in the periphery P-type regions, the first P-type region and the P-type second region, wherein numerous P-type extra sources also are formed on outsides of some of the N-type drains which are located in both the first N-type region and the second N-type region.
Another preferred embodiment of the invention is a four-transistor static-random-access-memory cell, which comprises: a first P-type transistor, a second P-type transistor, a first N-type transistor and a second N-type transistor. The first P-type transistor comprise a first P-type enlarged source, a first P-type enlarged drain and a first gate, wherein the distance between the second P-type enlarged source and the first P-type enlarged drain is larger than the width of the first gate. The second P-type transistor comprises a second P-type enlarged source, a second P-type enlarged drain and a second gate, wherein the distance between the second P-type enlarged source and the second P-type enlarged drain is larger than the width of the second gate. The first N-type transistor comprises a first n-type drain, a first N-type source, a third gate and a first P-type extra source, wherein the first P-type extra source is located outside the first N-type source, and the distance between the first N-type source and the first N-type drain is less than the width of the third gate. The second N-type transistor comprises a second n-type drain, a second N-type source, a fourth gate and a second P-type extra source, wherein the second P-type extra source is located outside the second N-type source, and the distance between the second N-type source and the second N-type drain is less than the width of the third gate. The second N-type transistor comprises a second n-type drain, a second N-type source, a fourth gate and a second p-type extra source, wherein the second P-type extra source is located outside the second N-type source, and the distance between the second N-type source and the second N-type drain is less than the width of the fourth gate, the second N-type source is electrically coupled with both the second P-type drain and the third gate and the fourth gate is electrically coupled with both the first P-type drain and the first N-type source.